In many technologies, digital data streams are transmitted without a clock signal. At the receiver end, the transmitted data has to be retrieved without losing its integrity with the accompanied timing information. In order to do this, the receiver generates a clock from an approximate frequency reference, and then phase-aligns to the transitions in the data stream with a phase-locked loop (PLL). This is referred to as clock-data recovery (CDR). A number of techniques have been developed to accomplish CDR. However, the existing techniques suffer from various disadvantages such as peak-to-peak jitter, inherent static phase offset, and inability to perform phase stepping.